This paper describes the history of Verilog HDL, including its influential predecessors and successors.

Verilog HDL is a hardware description language. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous gate-centric schematic techniques have transformed into textual register-transfer language (RTL) descriptions written in Verilog. By 2015 it is estimated that 80–90% of IC designs in the United States use Verilog and its compatible descendant SystemVerilog.

A hardware description language (HDL) is a variation of a programming language tuned to the overall needs of describing hardware. As such, an HDL has several key attributes that distinguishes it from a conventional programming language:

• Inherent parallelism: multiple simultaneous threads of operation, just like actual hardware
• Support for timing: sequencing of operations, delaying of signals, and an understanding of clocks
• Supremacy of the bit: allows abstraction to vector while maintaining full awareness of the underlying bits

Description of hardware using abstract notation such as Boolean algebra dates back to Shannon’s 1940 master’s thesis. Arguably the first true HDL was a “register transfer language” used by Irving S. Reed in 1956 to describe the design of a digital computer. Research and development into hardware description languages continued through the 1960s. A 1974 survey listed over fifty HDLs from all over the world.

One of the most influential HDLs of that era was HILO, followed by HILO-2. Developed by a team at Brunel University, and led by Peter Flake and Gerry Musgrave, HILO was the first HDL to be marketed commercially. HILO-2, like many HDLs a mostly declarative language, supported not only gate-level and switch-level abstractions including explicit timing information, but also supported register-transfer level (RTL) descriptions. The simulator for HILO-2 was developed by Phil Moorby.

By 1983 Moorby had joined Gateway Design Automation, a startup founded by Prabhu Goel (who had been the first HILO customer in the US). Moorby was tasked with creating a new language to support logic synthesis, fault simulation for test, and logic simulation for design verification. During the month of December 1983, Moorby working with Chi-Lai Huang, specified this new language which came to be called Verilog. Moorby developed the Verilog logic simulator during 1984, and by early 1985 the product was available for sale. Verilog featured:

• Simplicity: Simple yet powerful syntax was attractive to hardware designers (many with little software engineering experience)
• Procedural style: To the heavily declarative style of HILO-2, Verilog added rich procedural elements with support for function calls
• HDL and testbench in one: In addition to pure hardware description, features of the language enabled sophisticated test benches
• Very fast multilevel simulator: Behavioral, gate-level, and switch-level constructs were all supported

Further improvements by Moorby led to the 1987 introduction of an even faster simulator named Verilog-XL, which had many additional features to support ASIC signoff. By 1988 another startup, Synopsys, had chosen Verilog as an input language for its synthesis product Logic Compiler (soon renamed Design Compiler). All the pieces were now in place for the coming “ASIC revolution” in hardware design.

Gateway was acquired by Cadence Design Systems in 1989. Soon thereafter Cadence placed Verilog HDL into the public domain, and the language was managed and promoted by the independent Open Verilog International (OVI). Verilog became an IEEE standard in 1995 and by then was in widespread use by ASIC vendors and designers. Significant enhancements were made to the language in its 2001 IEEE standard.

After over a decade of extensive use, and as hardware designs and testbenches became larger and more complex, Verilog began to expose its limitations. There was much speculation of replacing HDLs altogether, instead using C++ or Java for hardware design. However, the existing and enthusiastic base of Verilog designers were reluctant to give up their favorite language.

Another possibility was to keep the strengths of Verilog while extending the language. Simon Davidmann and Peter Flake took this approach with their new language Superlog, which was a strict superset of Verilog. In 1997 Flake and Davidmann founded Co-Design Automation to design and implement Superlog and its simulator. Superlog was intended as a single language for system specification, hardware design, and hardware verification. With significant industry support, much of Superlog along with original Verilog HDL and the Vera verification language were combined into a new language called SystemVerilog.

In 2005 SystemVerilog became an IEEE standard as a unified hardware design, specification, and verification language. SystemVerilog, with its roots stretching back over 40 years, continues to be today’s predominant language for large-scale digital design.